Advanced packaging technology is one of the most critical technologies in semiconductor industry in recent years based on two reasons. Firstly, to continue drive device (or chip) scaling following Moore’s law is now more challenging than ever. Manufacturing cost increases rapidly so that the chip scaling becomes less viable economically. Chip partition plus system integration of multiple chips with a SiP, System-in-Package, advanced packaging technology, has been proposed to either replace or to be complementary to conventional chip scaling, to achieve system scaling. On the other hand, new semiconductor market demands driven by smart mobile
computing, cloud computing and Next Big Things (wearable, IoT, etc) are pushing existing packaging technologies, such as wire-bonding, flip-chip, multi-chip-module (MCM) and package-on-package (PoP), beyond their limitation. Innovative advanced packaging technologies are desirable to meet future semiconductor market needs.
Very stringent requirements on maximized system performance (computation speed and memory bandwidth) with minimum consumed power, occupying smallest component area (or form factor), and using most competitive cost have to be fulfilled in order to meet the system demands described above. TSMC has initiated and developed innovative wafer-level-system-integration (WLSI) platform technologies, which include UFI (wafer-level chip
scale packaging, WLCSP), InFO (fan-out wafer-level-packaging, FOWLP) and CoWoS (Si Interposer, 2.5D) packaging technologies to meet the system requirements from low to high I/O pin-count applications. Since we proposed and delivered these technologies, they attract tremendous attention and become emerging new trend in semiconductor industry. In this paper, we will present the advanced electronic package materials employed in
those technologies and discuss their challenges and opportunities in the future.
Keywords: Advanced packaging materials, WLSI, 3DIC, Fan-out wafer-level-packaging, Silicon interposer