New chemical-mechanical planarization (CMP) processes for new materials planned to be used in building future IC devices are now in research and development (R&D). Early data on process trade-offs as well as on environmental, health, and safety (EHS) aspects were presented at the CMP Users Group (of the Northern California Chapter of The American Vacuum Society) meeting, held in Albany, New York on April 16 of this year in collaboration with the College of Nanoscale Science and Engineering (CNSE) SUNY Polytechnic Institute and SEMATECH.
Mike Corbett, principle with Linx Consulting, presented his company’s forecast on CMP consumable materials growth for both logic and memory. “We’re no longer in the era of 2D scaling. Right now the semiconductor industry is scaling through the use of novel materials and 3D structures. It started with memory cells going vertical for storage structures. All of these technologies rely on CMP as a key enabler: for 3D NAND there’ll be new tungsten, TSV need new copper, and transistors need CMP for high-k/metal-gate processing.”
Corbett estimates the current global market for pre-interconnect CMP consumables—slurries, pads, and conditioning disks—at >$US1.5B annually with steady growth on the horizon. While the fabricated cost/wafer at the leading edge is estimated to increase by 25-60% when moving to the next leading-edge node, the cost of CMP consumables should only increase by 12-14%. The Figure shows the specific example of 2D NAND wafer cost increasing by 60% in moving from 20nm- to 16nm-node production, while the fab’s CMP costs increase just ~12%. Until the IC HVM industry begins using materials other than Si/SiGe for transistor channels it seems that CMP costs will be well controlled.
Fig.1: Cost modeling shows that 2D NAND memory fab cost/wafer increases 65% when moving from 20nm- to 16nm-node production, while the cost of CMP consumable materials may increase only 12% for that fab. (Source: Linx Consulting)
Alternate channel materials toxicity in CMP
With alternate channel materials on the horizon for future logic transistor, III-V materials such as gallium-arsenide (GaAs), gallium-indium-phosphide (GaInP), and indium-phosphide (InP) are now in R&D which leads to questions regarding direct process costs as well as indirect EHS costs. Hsi-An Kwong, SEMATECH EHS Program Manager, provided an important overview of these issues in his presentation on “Out-gassing from III-V Wafer Processing.” Much of the concern involves the possible reaction and release of toxic hydrides such as arsine, and phosphine. SEMATECH worked with imec to monitor hydrides produced during CMP processes for high-mobility compound semiconductors.
With 1.5% H2O2 in a relatively low-pH slurry, phosphine was measured on the tool from InP but not from GaInP. Use of higher pH with the same 1.5% H2O2 resulted in no phosphine from InP, but arsine outgassing from GaAs. Use of the highest pH resulted in no outgassing of phosphine or arsine. “When we develop the CMP process, particularly when moving to HVM we need to study the layers on the wafer and the slurry used to evaluate if outgassing will be an issue,” explained Kwong. “FTIR is the metrology instrument needed to be able to distinguish between different evolved hydride species.” HVM fab personnel working on or near CMP tools would have to wear personal breathing apparatus if processes evolve hydrides; for example, the SEMATECH/CNSE continuous exposure EHS specification allows a maximum human exposure level of just 1.25 ppb arsine.
In technical sessions at SEMICON West in San Francisco last year, SEMATECH presented on EHS issues with CMP of III-V materials in high-volume manufacturing (HVM). Toxic hydride gases evolve during direct CMP and during over-polish of contacts. Metallic arsenic could potentially build-up on tools over time, and will have to be treated in CMP waste water. To minimize risks, dedicated CMP tools will likely be needed for R&D and for HVM.